1. Field of Invention
The present invention generally relates to a voltage integrating circuit, and more particularly to the voltage integrating circuit with a low gain and/or low speed operation amplifier.
2. Description of Prior Art
Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional voltage integrator 100. The voltage integrator 100 includes a capacitor C1 and an operation amplifier OP1. The operation amplifier OP1 has a positive input end, a negative input end and an output end. The positive input end of the operation amplifier OP1 receives a reference voltage Vref. The capacitor C1 is coupled between the negative input end and the output end of the operation amplifier OP1. The negative input end of the operation amplifier OP1 receives a current IIN, and the output end of the operation amplifier OP1 generates an output delta Vout.
In the operation of the voltage integrator 100, the current IIN flows into the negative input end of the operation amplifier OP1, and the output voltage Vout on the output end of the operation amplifier OP1 may be presented as formula (1):Output delta Vout=IIN×C1×t+Vneg  (1),wherein, t is time.
If a gain of the operation amplifier OP1 is high enough (i.e. <60 db), the voltage Vneg on the negative input end of the operation amplifier OP1 is almost equal to the reference voltage Vref, so the output delta Vout=IIN×C1×t+Vref. However, if the gain of the operation amplifier OP1 is not high enough, the output delta Vout=IIN×C1×t+Vref+Voffset, wherein the voltage Voffset is an offset voltage of the operation amplifier OP1.
When the current IIN flows into the operation amplifier OP1, the output voltage Vout may be pulled down (or up) by the output stage of the operation amplifier OP1. If the operation amplifier OP1 does not have high gain or a response time of the operation amplifier OP1 is slow, the operation amplifier OP1 will has a variable voltage Voffset, and the performance of the voltage integrator is reduced correspondingly.